Besides the data oriented classification based on types Objective VHDL additionally provides a structural classification based on VHDL design entities: the entity classes.
VHDL entities already provide some features expected from an object-oriented class, like
- strong encapsulation (only ports and generics are visible outside),
- separation of declaration (entity) and implementation (architecture),
- the possibility to declare methods (subprograms) in the class declaration (entity) with implementation in the architecture,
- and the possibility to define attributes (signals, shared variables) in the entity or architecture.
Objective VHDL adds inheritance to entities and architectures in order to extend design entities towards object-oriented classes.
Yet, the Objective VHDL entity classes do not provide the whole set of object oriented concepts. Polymorphism as well as a predefined message passing concept are not available, but we will propose some ways to realize them.
Thus, considering entity-architecture pairs as classes is a very intuitive way of applying the classification concept, especially to hardware designers who are familiar with standard VHDL. Entity classes represent the structural classification of hardware and allow to apply the paradigm of hierarchical decomposition of functional units.
The fundamental differences of entity classes compared with type classes are the concurrency of entity classes and their active behavior.